1. Technical Field
The invention relates to a semiconductor device and a method of manufacturing the semiconductor device. The invention is a technology that may be applied to, for example, a semiconductor device having a nitride semiconductor layer and a method of manufacturing the semiconductor device.
2. Related Art
In recent years, semiconductor devices having various structures have been suggested so as to improve characteristics of semiconductor devices formed from a nitride semiconductor.
Japanese Unexamined patent publication NO. 2010-109086 discloses the following semiconductor device. A second semiconductor layer of an undoped nitride semiconductor is provided on a first semiconductor layer of a p-type nitride semiconductor. A third semiconductor layer of an undoped or n-type nitride semiconductor is selectively provided on the second semiconductor layer. An insulating film is provided on the second semiconductor layer. In addition, a control electrode is provided on the insulating film so as to be located between a first main electrode and a second main electrode. A bandgap of the third semiconductor layer is larger than that of the second semiconductor layer. It is described that a normally-off type nitride semiconductor element having a low on-resistance may be provided according to this configuration.
In addition, Japanese Unexamined patent publication NO. 2009-170546 discloses the following semiconductor device. n-AlGaN layers are formed on a p-GaN layer to be located immediately below a source electrode and immediately below a drain electrode. A channel layer is formed in the p-GaN layer and between the n-AlGaN layers. An insulating layer and a gate electrode are formed on the channel layer. It is described that a normally-off type GaN-based semiconductor device, in which contact resistances between the source electrode and drain electrode, and the n-AlGaN layers are lowered, may be provided according to this configuration.
In addition, Japanese Unexamined patent publication NO. 2009-164235 discloses the following nitride semiconductor element. The nitride semiconductor element is a vertical transistor. A nitride semiconductor laminated structure unit is provided on one side of an n-type substrate. In the nitride semiconductor laminated structure unit, an n-type GaN layer, a p-type GaN layer, and an n-type GaN layer are formed on the substrate in this order. A recess is formed at the center of the nitride semiconductor laminated structure unit to expose the lower side n-type GaN layer. A gate insulating layer and a gate electrode are formed at the recess. A drain electrode is provided on the other side of the substrate. A source electrode is provided on the upper side n-type GaN layer. It is described that a resistance value may be effectively decreased according to this configuration.
In addition, Japanese Unexamined patent publication NO. 2002-184972 discloses the following transistor. A GaN buffer layer, an i-type GaN layer having an electric resistance that is equal to or more than 1×106 Ω/cm2, and an i-type AlGaN layer are formed on a semi-insulating substrate. An undercut portion formed by digging the i-type GaN layer is formed in a lower portion of the periphery of the i-type AlGaN layer. The n-type GaN layer is provided to bury the undercut portion and a leg portion of the i-type AlGaN layer. A gate electrode is provided on the i-type AlGaN layer. A source electrode and a drain electrode are provided on the n-type GaN layer in such a manner that the gate electrode is interposed between the source and drain electrodes in a plan view. It is described that even when a gate bias voltage is 0 V, a pinch-off state may be realized.
In addition, Japanese Unexamined patent publication NO. 2006-100455 discloses the following nitride semiconductor device. A first nitride semiconductor layer and a second nitride semiconductor layer not containing Al are formed on a substrate in this order. A recess is formed on the second nitride semiconductor layer in such a manner that the first nitride semiconductor layer is exposed. A control electrode (gate electrode) that comes into contact with the first nitride semiconductor layer is provided in the recess. A source electrode and a drain electrode are provided on the second nitride semiconductor layer in such a manner that the control electrode is interposed between the source and drain electrodes in a plan view. Here, the second nitride semiconductor layer is formed by a Metal Organic Chemical Vapor Deposition (MOCVD) at a growth temperature lower than that of the first nitride semiconductor layer. In addition, it is disclosed that the second nitride semiconductor layer is formed with a microcrystalline structure. In addition, paragraph 0061 of Japanese Unexamined patent publication NO. 2006-100455 discloses that the second nitride semiconductor layer is a layer having a high insulation property. It is disclosed that the semiconductor device is made to realize a high withstanding voltage and thus a frequency dispersion of the semiconductor device may be suppressed.
In addition, Japanese Unexamined patent publication NO. 2004-228481 discloses the following compound semiconductor device. An electron transit layer formed from GaN, an electron supply layer formed from n-type AlGaN and a cap layer formed from n-type GaN are disposed on a substrate in this order. Source-side and drain-side recess portions, which are formed by removing at least a part of the thickness of the cap layer, which have a surface roughness more than that of the cap layer under the gate electrode, are provided on both sides of the gate electrode. A source electrode is disposed on the source-side recess portion. A drain electrode is disposed on the drain-side recess portion.
In addition, Japanese Unexamined patent publication NO. 2007-305954 discloses the following field effect transistor. A carrier transit layer is formed in a laminated structure in which a plurality of nitride semiconductor layers are provided, and a gate electrode, a source electrode, and a drain electrode are provided on the laminated structure. The laminated structure has a stepped portion having side surfaces, which expose end portions of the carrier transit layer, on both sides of the gate electrode. A source electrode and a drain electrode to which at least end portions of the carrier transit layer are connected are provided at the side surfaces of the stepped portion.
In addition, Japanese Unexamined patent publication NO. H09-330916 discloses the following method of etching a nitrogen-based compound semiconductor. An etching gas is composed of a mixed gas of a first gas that is at least one of a hydrogen gas and an inert gas, and a second gas that is at least one of a halogen gas and a halogen compound gas. A partial pressure of the second gas is within a range of several Torr to the normal pressure. The nitride-based compound semiconductor is etched using the etching gas at a temperature equal to or higher than 400° C.